Integration Technology of PC-FUSI (Phase Controlled FUSI) / HfSiON Gate Stack for Embedded Memory Application

Fabrication process of phase controlled FUSI (PC-FUSI)/HfSiON gate structure for small SRAM cells formation is proposed. The critical issue is controlled NiSi/Ni 3 Si boundary formation between the N-FET and P-FET gate electrode within a narrow STI region with wide process margin. This was realized by adopting a hard mask process to selectively form N/P-FET FUSI under tuned sintering condition. Suitable V th for LSTP devices, +/-0.45 V, and good transistor performance, I on =550/310 muA/mum at I off =20 pA/mum, were obtained with L g =55 nm. Operation of 0.446 mum 2 SRAM cells was confirmed even at 0.8 V with a static noise margin of 181 mV. We also discuss suitability of a PC-FUSI/HfSiON gate for embedded DRAM cell transistors.