Flexible associativity for DRAM caches

Applications continue to increase their capacity requirements. Die-stacked DRAM caches have been proposed as a solution to filter as many accesses as possible to main memory. DRAM caches have been predominantly studied in the scenario where the next level of memory is off-chip DRAM. With similar access times for both of these levels of the memory hierarchy, the focus has been optimizing access latency, rather than increasing the hit rate. Emerging non-volatile memory (NVM) technologies are proposed as an affordable solution to replace DRAM. These technologies come with a significantly higher access latency than an already slow DRAM. Thus, architects must reconsider design choices for DRAM caches. It is no longer reasonable to compromise on hit rate, and it is still necessary to mitigate access latency. In this work, we revisit the idea of associativity for DRAM caches. We propose Flexible Associativity (FlexA), a low-cost technique that allows the DRAM cache to behave as a low-access latency direct-mapped design for most accesses, but provides associativity when needed to optimize hit rate. We evaluate (FlexA) on a wide variety of workloads as well as in the presence of different main memory latencies. FlexA achieves an average speedup of 13% compare to the state-of-the-art work.