Non-Memoryless vs. Memoryless Hardware Architectures for Convolutional Neural Networks

This work presents two hardware architectures for convolutional neural networks. The designs are concise, allowing for their implementation using programmable devices taking advantage of the high degree of parallelism and component reuse. Two different approaches are used: one architecture requires memory, while the other eliminates this need by exploiting a different sequencing pattern for the data processing. In the latter, it is possible to store only one intermediate result per network channel. We show that even when implemented on simple reconfigurable devices and using fixed-point precision, the proposed designs achieve low power, short processing time, and high hit rates, which are comparable to the hit rates obtained by a software implementation.