Design and Implementation of Bluetooth Low Energy Link Layer Controller Using Dataflow Programming

This paper presents the design of Bluetooth low energy (BLE) link layer controller implemented on application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) and general purpose processor (GPP). CAL dataflow programming has been used that allows automatic RTL and C code generation from high-level specification. The generated RTL code is synthesized and implemented on ASIC Silterra 180 nm process technology and Xilinx Artix FPGA, while the generated C code is implemented on Intel i7 GPP. High-level design space exploration has been made by performing actor merging techniques to obtain seven different architectures, which are compared in terms of performance, area, power and energy. The results show that energy improvements for ASIC, FPGA and GPP are 44.71%, 10.22% and 28.31%, respectively, through the design space exploration methodology.