Optimization of AICu Wiring Delay in Advanced CMOS Technology

Fluorinated high-density plasma and plasma-enhanced CVD SiO2 inter-metal dielectrics have been evaluated for 0.50- through 0.25- μm generation CMOS. Several integration issues are discussed, including the impact of fluorine-doped SiO2 on the yield, reliability, and RC delay of 0.7 - 1.8 μm pitch back-end-of-the-line AlCu/tungsten-stud wiring.