A 0.02-mm2 9-bit 100-MS/s Charge-Injection Cell Based SAR-ADC in 65-nm LP CMOS

This paper presents the first published 9 bit resolution charge-injection cell based area-efficient SAR-ADC (ciSAR). The ciSAR employs both, a charge pump technique as well as a charge balancing switching scheme during binary search. Herewith, the ciSAR achieves a maximum input differential swing of 1.4 V with 10 bit linearity up to the second Nyquist zone. Additionally, the non-linear comparator input capacitance is isolated from the track and hold function for linearity improvements during the top-plate sampling operation. The ADC is reference-free and features an intrinsic 4.5 dB gain tuning range with only minor SNDR and SFDR variations of less than 2 dB. Implemented in a 65nm LP CMOS process, the ADC reveals 7.5bit ENOB and 62 dBc SFDR up to second Nyquist zone. With an area of only 0.02mm 2 and an aspect ratio of 1:4, the ciSAR with 451 MHz effective resolution bandwidth enables highly parallel sensor readout systems.