Grain-Boundary Related Hot Carrier Degradation Mechanism in Low-Temperature Polycrystalline Silicon Thin-Film Transistors

Unique degradation behavior of transfer characteristics was observed in low-temperature (LT) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) after hot carrier stress. In the transfer characteristics, drain current was reduced markedly after stress at a gate voltage (VG) of more than the threshold voltage (VT), while it showed little change after stress at VG of less than VT. These phenomena cannot be explained by the generation of fixed charges in the gate oxide or gate-oxide interface trap charges. To understand this degradation mechanism, the stress-induced resistance RI is introduced, which is connected with the channel resistance Rchannel in series. The calculated RI values are systematically decreased with the increase in drain voltage (VD), which indicates that the degraded region is close to the drain edge near the surface. Moreover, RI values show exponential decay with the increase in VG, which implies the lowering of a potential barrier. A possible origin of RI is potential barriers caused by negative charges generated at the grain boundaries degraded by hot carrier attack.