A 360–456 MHz PLL frequency synthesizer with digitally controlled charge pump leakage calibration

A charge pump leakage current calibration circuit has been proposed for the phase-locked loop frequency synthesizer. A digitally controlled feedback loop has been built for the adaptive calibration. A 360–456 MHz ring oscillator based fractional-N PLL has been designed and fabricated in 65 nm CMOS technology. The prototype chip occupies a die area of 0.064 mm2, and consumes 1.11 mA current from a 1 V supply. Measurement results show that the reference spur is suppressed by 25 dB with the leakage calibration enabled, when outputting 432 MHz clock. The relative level of the reference spur is at least 10 dB lower that other designs in literature.