High-Performance Tunnel FETs on Advanced FDSOI Platform

In this chapter, we present Tunnel FETs (TFETs) obtained with a FDSOI CMOS process flow featuring High-K Metal Gate, ultrathin body compressively strained Si1-xGex (x from 0 to 30 %) based channels, and Si0.7Ge0.3 Raised SD. In-depth characterizations have been conducted to analyze the device structures (TEM, EELS for atom/layer identification, HAADF STEM GPA for strain) and device electrical performance (C(V), I D (V G ) vs. V DS and temperature, I ON , S w , tunnel extractions…). We investigate the tunneling improvements due to the different technological injection boosters: ultrathin body and gate dielectrics, strain, low band gap source, and low temperature SD anneal. The impact on I D (V G ) curves and thus on ON (and OFF) state current, subthreshold slope is presented and discussed. For the first time, TFETs with large ON current (up to 428 µA/µm) are demonstrated (with >×1,000 I ON gain vs. SOI TFETs, and >×35 I ON gain vs. best published pTFETs). Future paths towards further enhanced TFET devices are also detailed.