A 51K-gate low power ECL gate array family with metal-compiled and embedded SRAM

A family of 80 ps, 1 mW/gate series-gated ECL (emitter coupled logic) gate arrays of up to 51K-gate density is described. The family supports both metal-compiled SRAM (static random-access memory) with a typical TAA of 2.5 ns and embedded SRAM with a TAA of 2.0 ns. Raw core densities of 1125 gates/mm/sup 2/ are achieved using a true ocean-of-cells, channel-less architecture. The arrays are fabricated using the ASSET-1 (all spacer-separated element transistor) 2-poly, 3-layer metal process with a conservative 1.2 /spl mu/m emitter lithography.