Design of a High-Performance 2-bit Magnitude Comparator Using Hybrid Logic Style

Design of a 2-bit binary Magnitude Comparator (MC) is presented in this research. The proposed MC has been designed using Conventional CMOS (CCMOS) logic, Pass Transistor Logic (PTL). The design is simulated along with 5 other existing MC designs in order to carry out evaluation and comparison. The proposed 2-bit MC displayed satisfactory level of improvement in speed and power. For this reason, significant enhancement in Power Delay Product (PDP) could have been attained. Due to the significant enhancement in performance, the proposed MC can be considered as a highly effective alternative to the existing MC designs.