Applications of Hardware Implementation of P Systems

It is a long-cherished wish to implement numerical P systems (NPS) on a parallel architecture so that its large-scale parallelism can be exploited to speedup computation tremendously. Field-programmable gate array (FPGA) is a reconfigurable hardware in which operations are triggered so synchronized by edge or level of activating signals, making it an eligible platform to implement NPS and its variant, enzymatic numerical P system (ENPS). In this chapter, (E)NPS-based robot controllers and path planning algorithm are implemented in FPGA, achieving a speedup of 105 and 104 order of magnitude compared to software simulation. FPGA hardened (E)NPS in this research can be regarded as a heterogeneous multicore processor since membranes inside work as processing units which possess different functions.