Solutions for logic and processor core design at the 45nm technology node & and below

In this paper we present an overview of techniques and methodologies for processor cores and digital SoC integration showing how process sensors, circuitry and system control cooperate in order to achieve the best power, performance, area and yield trade-off. We cover combinatorial and sequential logic as well as memory cores in the context of retention, power gating and adaptive features. Various techniques are also given as example and illustrated by silicon measurements.