Positive bias instability in gate-first and gate-last InGaAs channel n-MOSFETs

Instability under positive bias stress in the InGaAs channel n-MOSFETs with gate last Al 2 O 3 and gate-first ZrO 2 /Al 2 O 3 process flows is investigated. It is determined that the threshold voltage shift (ΔV T ) during stress is primarily caused by a recoverable electron trapping at the pre-existing defects located predominantly in the Al 2 O 3 interfacial layer (IL). Generation of new electron trapping defects is found to occur in the dielectric region adjacent to the substrate, while trap generation in the high-k bulk is negligible.