al-Oxide-Semiconductor Field Effect Tr hreshold Swing and Internal Voltage Am

This work reports the experimental demonstration and in subthreshold swing, SS, smaller than 60 room temperature, due to internal voltag in FETs with a Metal-Ferroelectric-Me stack. The investigated p-type MOS t dedicated test structure to explore capacitance effect by probing the in between the P(VDF-TrFE) and SiO2 diel the gate stack. We find that the region of i potential amplification, dψS/dVg>1, corr S-shape of the polarization versus ferro (associated with negative capacitance). I internal voltage amplification could sign their SS, even without reaching sub-60 SSmin as low as 46 to 58 mV/decade and a SSavg, as small as 51 to 59 mV/dec are ob first time in a minor loop hysteretic ch Fe-FETs.