ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08µm 2 SRAM cell

For the first time we report extremely thin SOI (ETSOI) CMOS with 22 nm gate length (L G ) and sub-100 nm contacted gate pitch for system-on-chip (SoC) applications. Multi-V t transistors are demonstrated with competitive drive currents (NFET/PFET) of 1150/1050 µA/µm at I off = 100 nA/µm for high performance (HP) and 920/880 µA/µm at I off = 1 nA/µm for low power (LP), respectively, at V DD = 1 V. High density 6-T SRAM cells down to 0.08 µm 2 are demonstrated. Compared with a 28nm bulk LP technology, the high drive currents of ETSOI transistors coupled with large capacitance reduction by aggressive L G scaling result in 25% improvement in ETSOI ring oscillator (RO) speed. Auxiliary ETSOI devices including epitaxy resistors with high precision and gated diodes with near ideal characteristics are fabricated to complete device menu for early ETSOI SoC design.