A 1 V, 39 μ W, 5-bit Multi-Level Comparator based Flash ADC

This paper proposes a multi-level comparator based Flash ADC architecture. The proposed design reduces the complexity of the quantizer by using a single multi-level comparator consisting of multiple reference branches. The reference voltages connected to these branches are compared with the input voltage. The architecture is designed in a 65-nm CMOS technology with a supply voltage of 1 V. The architecture consumes a power of $39 \mu \mathrm{W}$ with an effective number of bits of 4.95 bits. The proposed design has an Figure of merit (FoM) of 13.62 fJ/conv-step. at a sampling frequency of 100 MHz. The maximum sampling frequency of the design is 250 MHz.