First ultra-thin film FDSOI devices with CMP-less TOtally SIlicided (TOSI) gate Integration

In this paper we present a study of the integration of a TOSI gate process on fully-depleted SOI devices by using a CMP-less approach and a detailed electrical characterization of NMOS and PMOS transistors, including transport properties. Tuning of the workfunction has been observed for the NMOS devices by doping the polysilicon before gate silicidation. Functional PMOS and NMOS devices have been tested down to 50nm gate length. PMOS devices exhibits very good Ion/Ioff performances (Ion: 492?A/?m at Ioff: 25nA/?m @ Vdd ?1.2V) despite the relatively thick gate oxide thickness used. The inverters' functionality of the FDSOI SRAM cell with a size of 0.99?m2 has also been demonstrated, reflecting that this technology is a very promising candidate for 45nm LP node and beyond.