10T Differential-Signal SRAM Design in a L4-NM FinFET Technology for High-Speed Application

This paper describes a high-speed memory design with a 10-transistor (10T) differential-signal SRAM cell in a 14-nm FinFET technology. The 10T SRAM cell is 2.63 times larger than the smallest 6 $T$ HD SRAM cell for this technology. With silicon-validated device models and back-annotated netlist, parasitic capacitances on BL and WL show 23% and 72% increase vs. 6 $T$ HD bitcell, respectively. Even with higher parasitic capacitance, when 20% WL overdrive is available, a 10T 64×64 array can operate 52% faster than a 6T under worst-case conditions for the proposed evaluation array scheme. For the 10T architecture, increasing the number of read-out fins results in small operating speed improvement due to increasing parasitic capacitance. So, a 4-fin read-out bitecell results in only 6% faster operation than a 2-fin implementation.