Single-ended transceiver design techniques for 5.33Gb/s graphics applications

Graphics processing is the driving force behind the demand for high-bandwidth DRAMs. Accelerating the pace of bandwidth improvement, fifth-generation graphics DDRs will operate at data rates up to 5.33Gb/s, and support single-ended signaling for low pin-count. A significant design challenge is to ensure proper signal transmission over single-ended wires at rates previously attainable only with differential pairs. We present single-ended transceiver design techniques for 5.33Gb/s operation. In addition to the receiver and transmitter, a CML-to-CMOS converter and an integrated serializer/level-shifter are described (Fig. 7.5.1). The circuits are fabricated in 0.13µm 1.2V CMOS. The chip area is 5.7×7.0mm 2 and is housed in a quadratic BGA package with 289 balls.