Electrical Coupling of Monolithic 3-D Inverters

In this brief, we investigate the electrical coupling between stacked field-effect transistors (FETs) in monolithic 3-D inverters (M3INVs). We study the range of interlayer dielectric (ILD) thickness ( $T_{\text {ILD}}$ ) and channel length $L_{g}$ values that lead to a strong coupling between stacked FETs. Our device simulations show that M3INVs with $T_{\text {ILD}} \geq 50$ nm lead to negligible interaction between the stacked FETs. In addition, our 3-D mixed-mode circuit simulations show that the switching threshold voltages, propagation delays, and fall times of M3INVs with $T_{\text {ILD}} nm are significantly affected by other tiers. This means that new circuit simulation techniques that consider the electrical coupling between the stacked devices are required in monolithic 3-D integrated circuits.