A Body-Biasing Technique for Single-Event Transient Mitigation in 28 nm Bulk CMOS Process

Single-event transient (SET) glitches can be modified by body-biasing controlling techniques. In this paper, a body-biasing configuration is proposed in combinational circuits, which plays no role during devices’ normal operation, but significantly mitigates SET disturbance as ion strike happens. NOR cell chains and NAND cell chains are served as cases to investigate the impact of the proposed configuration on SET vulnerabilities under two groups of heavy-ion experiments. Experimental data illustrate that transistors with body tied to source (BTS) significantly reduce the SET cross-section compared to the normal designs. The physical mechanism of the proposed technique is quantitatively analyzed in detail.