Enhancing die level static fault isolation on power gated devices

Abstract Modern SoC design incorporates power management circuits to minimize standby leakages of digital logic circuitry. This isolates the logic blocks from being directly powered by the IC's pad level power supply and ground. As a result, die level static fault isolation became ineffective even for gross defects that are shorting the power lines in the logic blocks due to gated supply. From the foundry standpoint, fault isolation on such devices are even more challenging without the product knowhow, device specific hardware and test program to properly condition the power management circuits. An alternative method is to bypass the power control circuits through microprobing on the top metal traces to directly supply power to the logic blocks. However, the key challenge to this method is the means to differentiate between power gated and non-gated devices and then subsequently verify the relevant power traces to microprobe especially in the absence of layout. This paper illustrates 4 different approaches to overcome this challenge and achieve static fault isolation success on power gated devices. Successful applications of this approach to localize gross defects resulting in short/leakage failures and subtle defects resulting in memory/logic functional failures will be described.