VLSI Implementation of High Speed Programmable Duty Corrector for All Digital Applications

Double Data Rate (DDR) memory used for speedy data transmission applications such double sampling analog-to digital converter, the up and negative edges of the structure clock are utilize for data sampling. Thus, these systems involve a correct 50% duty sequence of the system clock. The two wide ranges All Digital Duty Cycle Correctors (ADDCC) with output clock Phase Alignment are here. The proposed phase alignment (PA) ADDCC not only realizes the preferred output/input PA, but as well continues the output duty cycle at 50% with a round locking time and High-Resolution (HR) ADDCC without a half cycle delay line can improve the interruption resolution and the delay mismatch problem. Glitch free NAND-base DCDL which overcome this control by opening the take up of NAND-based DCDLs in a wide range of applications DCDL continues the matching resolution and minimum delay NAND-based DCDL.ADDCC is implemented in an all-digital manner to decrease circuit complexity and leakage power in advanced development technologies and, thus, are very proper for system-on-chip (soc) applications.