Design methodology of tri-gate poly-Si MOSFETs with 10nm nanowire channel to enhance short-channel performance and reduce V th & I d variability

We present the optimum design of tri-gate poly-Si nanowire transistors (NW Tr.) based on the systematic performance and variability analysis for various NW width (W NW ) and thickness (T Si ) down to 10nm. I on difference between poly-Si and crystalline-Si Tr. at short L (down to 25nm) is much smaller than long L due to poly-Si defect-barrier lowering by high lateral field. I on of poly-Si pFETs is close to nFETs due to smaller interface defects. Both W NW and T Si scaling reduces S factor, SCE and A vt (V th & I d variations) caused by random grain placement. A vt of thin poly-Si Tr. falls even below doped bulk Tr. Since short-NW Tr. suffers from high R SD and low μ, narrow and tall poly-Si NW Tr. is the best for 3D CMOS.