A wafer scale fail bit analysis system for VLSI memory yield improvement

A wafer-scale fail bit analysis system which outputs an entire wafer fail bit map (FBM) by using a data compaction technique and testing structure is developed. With this system, process defect locations on a wafer can easily be electrically recognized quickly. The processing time of wafer-scale fail bit analysis is reduced to only 2% of that required by the conventional method. An example of a wafer-scale FBM is shown. >