Scalable fully coupled annealing processing system and multi-chip FPGA implementation

This work proposes a scalable method for a large-scale fully coupled annealing processing system that utilizes multi-chip operation in parallel to solve the combinatorial optimization problems facing a wide range of applications. We previously proposed an architecture for the LSI implementation of a fully coupled annealing processor that updates the value of spin based on an energy calculated using a one-dimensional spin array and a two-dimensional spin-to-spin interaction array. In the present work, expanding this method, we proposed a new method of dividing the energy and calculating it on several identical first chips and then taking the sum of them on a second chip to obtain the updated spin value. The amount of data communication between the first and second chips is quite small with only 4 pins used for chip connection each. This enables us to create a fully coupled annealing processing system with a scalable number of spins. The results of an FPGA demonstration confirmed that these small amounts of communication by multi-chip operation were possible while operating as a fully coupled system. In the demonstration, a 384-spin fully coupled annealing processing system board was implemented using 16 first FPGA chips and one second FPGA chip. The current consumption of the entire system board was 950 mA when idling and 1050 mA when running fully coupled annealing processing at 10 MHz. The results also showed that a 92-node graph coloring problem and 384-node max-cut problem could be solved by using this system. For the max-cut problem, our system board was 584 times faster and 46 times more energy efficient than a 4-GHz CPU PC when solving the same problem.