Si Surface Orientation Dependence on the Electrical Characteristics of HfN Gate Insulator with sub-0.5 nm EOT Formed by ECR Plasma Sputtering

This paper investigated the silicon substrate orientation dependence on the electrical properties of high-κ HfN gate insulator formed by electron-cyclotron-resonance (ECR) plasma sputtering. The effect of N2/4.9%H2 forming-gas annealing (FGA) was studied. By using N2/4.9%H2 FGA at 500°C for 20 min, the interfacial layer (IL) formation was not formed and led to the zero-interface layer (ZIL). The EOTs of 0.47 and 0.51 nm with leakage current of 1.1 and 1.4 A/cm (@VFB -1 V) were obtained on p-Si(100) and p-Si(110), respectively. The density of interface states (Dit) with the order of 10 cmeV was obtained on both p-Si(100) and pSi(110). This suggests that the direct deposition of HfN film with ZIL prevented the degradation of electrical characteristics on the p-Si(100) and p-Si(110) substrate in comparison to the case of oxide-based hafnium gate insulator. INTRODUCTION For over 50 years, the scaling of the metal-oxide-semiconductor field effect transistors (MOSFETs) have continuously kept on track with Moore’s law, where the density of transistors integrated into a single chip has doubled every 18 months [1]. This scaling trend required the thinning of SiO2 gate dielectric below 2 nm which leads to a high direct tunneling gate leakage current [2]. To suppress the leakage current density (Jg) with small equivalent oxide thickness (EOT), alternative high dielectric constant (high-κ) materials such as HfO2 or HfSiON should be considered as a gate insulator instead of the conventional SiO2 gate dielectric [3]. However, an ultrathin low-κ interfacial layer (IL) normally forms at the interface of high-κ gate insulator and silicon substrate, and has limited the further scaling of EOT [4]. This infers that nitride dielectrics are good candidate materials for gate dielectrics to overcome the problems of oxidebased high-κ materials in suppressing IL formation and oxygen vacancy. Among the nitride dielectrics, the nitrogen-rich hafnium nitride (HfN) gate insulator formed by the electroncyclotron-resonance (ECR) plasma sputtering method shows excellent electrical properties with a 0.6 nm-thick EOT without the IL formation at the HfN/Si interface and obtained low leakage current using N2/4.9%H2 forming-gas annealing (FGA) on the p-Si(100) substrate [5, 6]. The use of N2/4.9%H2 FGA is due to the formation of Si-N-H bonding (hydrogen passivation) by nitrogen-hydrogen gas mixture, which can terminates the dangling bonds at the HfN/Si interface. It can attribute to decrease the density of interface states (Dit) and IL formation that can improve the properties and reliability of nitride/Si interface [7, 10]. The forming-gas mixture used throughout (5% of H2 in N2) was chosen to prevent explosive, and hence, can be carried out using inexpensive processing equipment [11]. As the dimensions of transistor are reduced, the three-dimensional (3-D) multi-gate FET structure is required to suppress short-channel effects (SCE). In 3-D MOSFETs, the different channel orientations, which are located at the sidewall surface and the top surface affected the IL formation and influenced to the electrical characteristics and reliability of the device [12]. Many researchers proposed that, by using oxide-based hafnium gate dielectric such as HfO2 and HfSiON, the unintentional IL formation and interface roughness can generate a thicker IL layer on p-Si(110) compared to p-Si(100). This IL also induces a higher EOT with a higher leakage current on p-Si(110) compared to p-Si(100) [13, 15]. This means, the suppression of the IL formation is required to reduce the degradation of electrical properties on p-Si(110). This paper presents the suppression of IL formation with EOT of 0.5 nm or below by using HfN gate insulator formed by ECR plasma sputtering. The influence of N2/4.9%H2 FGA condition including the annealing temperature and duration to the electrical characteristics of the HfN gate insulator were studied. The effects of surface orientation such as Si(100) and Si(110) were investigated for the 3-D MOSFETs. EXPERIMENTAL DETAILS The metal-insulator-semiconductor (MIS) diodes structure with HfN gate insulator were fabricated on both p-Si(100) and p-Si(110) substrates in accordance with the process flow shown in Fig. 1. First, the Si substrates were chemically cleaned by a sulfuric peroxide mixture (SPM) and diluted hydrogen fluoride (DHF) for two cycles. The rinsing time for the ultra-pure water (UPW) was fixed at 1 min to prevent surface roughness induction [14]. Before depositing the HfN film, the hafnium target was pre-sputtered by argon (Ar) plasma with a sputtering gas pressure of 0.16 Pa for 10 min. The aim of the pre-sputtering is to clean the hafnium target surface. The HfN film was then deposited on the Si substrate by ECR plasma sputtering at room temperature. Both RF power and μ-wave power were fixed at 500 W. The Ar/N2 gas flow ratio was fixed at 20/8 sccm, in which the nitrogen ratio was 28.8% with 1 minute sputtering time. By using the N2 flow ratio over 20%, the amorphous HfN film with an insulating property is obtained [15]. The deposited HfN film was annealed in N2/4.9%H2 forming-gas (FG) ambient with the flow rate of 1 SLM. The annealing temperature and duration were varied as 400°C/30 min, 500°C/20 min, 500°C/30 min, and 600°C/10 min, respectively. Finally, the top (φ = 94 m) and bottom Al electrodes were deposited by evaporation. The capacitance-voltage (C-V) and current-voltage (J-V) characteristics of the Al/HfN/p-Si MIS diodes were measured. A dualfrequency method was used to evaluate the C-V characteristics [16]. The EOTs were extracted by using the exponential potential based quantum mechanical extraction (EPOQUE) method [17]. The density of interface states (Dit) was evaluated by Terman method [18]. Figure 1. (a) Experimental procedure and (b) schematic cross-section of the Al/HfN/p-Si MIS diode. The top view of the fabricated diodes is also shown. p-Si sub. HfN Al Al p-Si(100), p-Si(110) substrate SPM+DHF cleaning (x2) HfN film deposition (ECR plasma sputtering) Ar/N2, 20/8 sccm, 0.20 Pa, 4 nm N2/4.9%H2 FGA (1 SLM) 400-600°C, 10-30 min Top (φ = 94 μm) and bottom Al electrodes evaporation C-V and J-V measurement 94 μm