Exploring alternative flexible OpenCL (FlexCL) core designs in FPGA-based MPSoC systems

Open Compute Language (OpenCL) has been proposed as a platform-independent parallel execution framework to target multicores, graphics processing units (GPUs), digital signal processors (DSPs), and other custom accelerators. Traditionally OpenCL is designed to scale across system generations by having each new model increase the available resources: processing cores, register file entries, and shared (localized) physical memory. However, when evaluating all potential models capable of running OpenCL the numerous performance trade-offs associated with these competing resources makes for a large exploration space. Specifically there are advantages to systematically analyzing the OpenCL parallel expressions to eliminate processor elements that constrain the overall design. We have designed an analysis tool for evaluating OpenCL kernels and the potential processor configurations in FPGA-based multiprocessor systems-on-chip (MPSoC) designs. The Flexible OpenCL (FlexCL) system determines integrated hardware-software customization opportunities related to processor design across sets of OpenCL applications. The paper provides an evaluation of various OpenCL components synthesized to FPGA-based multicore design alternatives.