Performance Analysis of ESD Structures in 130 nm CMOS Technology for Low-Power Applications

This paper addresses static as well as dynamic performance analysis of a standard ESD structure fabricated in 130 nm CMOS technology. The original design of the ESD structures was aimed at power supply voltage of 1.2 V and usage of grounded-gate NMOS and PMOS devices. We investigated the properties of the presented ESD structure using a lowered value of the supply voltage, since the target application will be within a low-voltage / low-power systems with V DD = 0.6 V and V DD = 0.4 V. The comparison of the measured and simulated data is carried out and discussed. The paper also deals with the development of a novel high-accuracy VerilogA model in order to use more realistic load created by real ESD structures.