A silicon-on-silicon packaging technology for advanced ULSI chips

A RISC (reduced instruction set computer) module for high-performance workstations has been made to demonstrate the advantages and technical feasibility of the silicon-on-silicon technology. The module consists of one 0.8-/spl mu/m CMOS CPU (central processing unit) one 0.8-/spl mu/m CMOS FPU, and six 1.0-/spl mu/m BiCMOS cache memories. The eight chips are attached on a 39/spl times/47 mm square silicon substrate with 120-/spl mu/m pitch flip chip bonding of 80-/spl mu/m-diameter tin-lead bumps. Two-layer interconnections for high-speed signals are formed with 20-/spl mu/m line and 80-/spl mu/m space on the silicon substrate. The conductors are 4-/spl mu/m thick gold formed by electroplating and the dielectric film is 10-/spl mu/m-thick polyimide. A decoupling capacitance of about 0.8 nF is formed in the substrate. The module was evaluated using reliability and functional tests. The reliability tests included thermal cycling, power cycling, and mechanical strength tests. The functional test was carried out by connecting the module to an IBM-PC/IF board and operating with a test program. Both evaluations were successful. >