Design of a Low-Power Low-Kickback-Noise Latched Dynamic Comparator for Cardiac Implantable Medical Device Applications

This brief presents a new architecture of dynamic latched regenerative comparator that suited for the cardiac implantable medical device applications. In this proposed architecture, the comparator is designed with low transistor count to reduce power dissipation. Also the proposed comparator has a positive feedback mechanism for achieving low kickback noise and high resolution. It is shown that the generated kickback noise is reduced a lot when compared with the other existing architectures. The proposed comparator is designed with an additional circuitry that provides extra shielding between the nodes of input and output to reduce the generation of kickback noise. The presented work is simulated using Mentor Graphics tools in 130 nm technology. The proposed work is designed well to suit the functionality with supply voltages ranging from 450 mV to 1 V.