A parallel collision detection VLSI processor for robotics using a content-addressable memory

Real-time collision detection is one of the most important intelligent processings in robotics. In collision detection, a large storage capacity is usually required to store the three-dimensional information on the obstacles located in a workspace. Moreover, high-computational power is essential not only in coordinate transformation but also in matching operation. In the proposed collision detection VLSI processor, the matching operation is drastically accelerated by using a content-addressable memory. A new obstacle representation based on a set of rectangular solids is also used to reduce the obstacle memory capacity. Parallel architecture using several identical processor elements (PEs) is employed to perform the coordinate transformation at high speed, and each PE performs coordinate transformation at high speed based on the coordinate rotation digital computation (CORDIC) algorithms. When 250 PEs are used, the performance is evaluated to be more than one million times higher than that of a 28.5 MIPS workstation. >