Computational modeling of process induced damage during plasma clean

When partially completed circuits come in contact with plasmas during integrated circuit fabrication, current from the plasma can potentially damage active devices on the wafer. A suite of computational models is used in this article to investigate damage to ultrathin (1.0–5.5nm) transistor gate dielectric (SiO2) during Ar∕O2 based plasma cleaning in a capacitively coupled plasma reactor. This modeling infrastructure includes a two-dimensional plasma equipment model for relating process control parameters to ion and electron currents, a three-dimensional model for flux density calculation within a circular via, an electrostatic model for computing potential across the gate dielectric, and a percolation model to investigate dielectric damage characteristics. Computational results show that when the plasma current comes in contact with the gate dielectric, the gate dielectric rapidly charges up and the potential difference across the dielectric saturates at the level necessary to support the plasma induced ...