SiO 2 Free HfO 2 Gate Dielectrics by Physical Vapor Deposition

HfO 2 layers, 25-A thick, were grown by cyclic Hf sputter deposition and room temperature oxidation steps on chemically oxidized Si(001). Subsequent in situ annealing and TiN deposition yield a high- $\kappa$ gate-stack for which the original 8-A-thick SiO 2 layer is eliminated, as confirmed by transmission electron microscopy. Transistors fabricated with this gate-stack achieve an equivalent oxide thickness in inversion $T_{\rm inv} =9.7$ A, with a gate leakage $J_{g} =0.8$ A/cm 2 . Devices fabricated without in situ annealing of the HfO 2 layer yield a $T_{\rm inv}$ which increases from 10.8 to 11.2 A as the oxidation time during each HfO 2 growth cycle increases from 10 to 120 s, also causing a decrease in $J_{g}$ from 0.95 to 0.60 A/cm 2 , and an increase in the transistor threshold voltage from 272 to 294 mV. The annealing step reduces $T_{\rm inv}$ by 1.5 A (10%) but also increases the gate leakage by 0.1 A/cm 2 (30%), and causes a 61 mV reduction in $V_{t}$ . These effects are primarily attributed to the oxygen-deficiency of the as-deposited HfO 2 , which facilitates both the reduction of an interfacial SiO 2 layer and a partial phase transition to a high- $\kappa $ cubic or tetragonal HfO 2 phase.