A 4MB on-chip L2 cache for a 90nm 1.6GHz 64b SPARC microprocessor

Dennis Wendell,J. Lin,Pradeep Kaushik,Suresh Seshadri,A. Wang,V. Sundararaman,P. Wang,H. McIntyre,S. Kim,Wen-Jay Hsu,Heechoul Park,G. Levinsky,J. Lu,M. Chirania,Raymond A. Heald,P. Lazar

A 4MB on-chip L2 cache for a 90nm 1.6GHz 64b SPARC microprocessor

2004

Dennis Wendell
J. Lin
Pradeep Kaushik
Suresh Seshadri
A. Wang
V. Sundararaman
P. Wang
H. McIntyre
S. Kim
Wen-Jay Hsu
Heechoul Park
G. Levinsky
J. Lu
M. Chirania
Raymond A. Heald
P. Lazar

A next-generation 1.6GHz 4-issue CPU supports high-end servers and has a 4MB L2 cache. The chip uses 315M transistors in a 90nm 8M CMOS process with an area of 234mm/sup 2/.

Keywords:

Reduced instruction set computing
Computer science
CMOS
Parallel computing
Transistor
Chip
Microprocessor
Server
CPU cache
Computer hardware
cmos process

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