0.5-V high-speed circuit designs for nanoscale SoCs — Challenges and solutions

Some solutions are proposed and evaluated by simulation after the challenges facing the creation of 0.5-V nanoscale SoCs are clarified. First, the repair techniques and nanoscale FD-MOSFETs are discussed in terms of their V t -variation. Second, 0.5-V dual-V DD dual-V t logic circuits with gate-source reverse-biasing schemes are proposed. Third, a boosted word-voltage six-transistor (6-T) SRAM cell is evaluated with a 25-nm planar FD-SOI MOSFET and then a FinFET, revealing that the FinFET drastically improves the voltage margin and speed of the 6-T cell. Finally, the feasibility of a 0.5-V 25-nm SoC comprising a 1-Gb SRAM and 160-Mgate logic block is studied. We conclude that an SoC like this with a competitive speed while reducing the power to about one-tenth that of a conventional 1-V 32-nm CMOS LSI is possible, if the above-described devices and circuits are used and the within-wafer V t -variations are stringently controlled and/or compensated for.