Generalized Very High Throughput Unrolled LDPC Layered Decoder

Unrolled layered LDPC architectures have been shown to obtain tens of Gbps throughputs. These types of decoders are well suited to array LDPC codes, for which they present improved throughput. In this paper, we propose a generalization for unrolled layered LDPC decoding architectures, by employing the residue-based layered scheduling when merging multiple layers. This way, we can efficiently implement unrolled decoding architecture for any QC-LDPC (Quasi-Cyclic LDPC) codes. FPGA implementation results for WiMAX Rate 5/6 show that 35–41 Gbps throughputs are achievable using this architecture.