FPGA Implementation of 16 bit RSA Cryptosystem for Text Message

The rapid growth of the internet and electronic commerce has brought to the forefront the issue of privacy in electronic communication. In order to protect the information from unauthorized parties we need to mask the information before sending it through a communication channel. Currently RSA is one of the algorithms which are not broken by hackers due to its mathematical complexity. This paper presents a design and implementation of 16-bit RSA Cryptosystem. The entire cryptosystem is divided in to three parts: key generation, encryption and decryption. The key generation is carried out by using random number generator LFSR, “Sieve of Eratosthenes” algorithm for prime number detection, Booth multiplier for multiplication and Extended Euclidean algorithm to find GCD of the public key and Euler‟s Totient Function. Encryption and decryption is carried out by Modular Multiplication and Modular Exponentiation by using LR binary method. The encryption and decryption of the text message “NAGARJUNA COLLEGE” is verified using proposed RSA algorithm. The design is simulated using Modelsim10.2b simulator and finally implemented on Sparten-6 FPGA using Xilinx 13.4 software. Area and timing parameters are computed with respect to Spartan-6 FPGA. The results obtained from simulation are validated using MATLAB code.