Effective hardware implementation of Volterra filters based on reduced-rank approaches

The focus of this Letter is on the development of a new effective approach for the hardware implementation of Volterra filters. The proposed approach is based on exploiting the different significance levels of the branches in a reduced-rank Volterra implementation aiming to reduce the complexity required for implementing each branch. In this Letter, the probability of overflow is used as a metric to define individual word lengths for the fixed-point implementation of each branch. Experimental results corroborate the capability of the proposed approach for obtaining precise implementations with considerable reduction in computational complexity.