A systematic methodology to improve yield per area of highly-parallel CMPs

Manufacturing yield of chip multi-processors (CMPs) has become a significant problem as more transistors are integrated onto a single die, and the defect rate keeps increasing for "end-of-Moore" nano-scale CMOS technologies. Since such CMP designs usually have significant structural symmetry, adding spares to these should be an effective method for increasing yield per area, as is the case for memories. However, a systematic approach to add spares to optimize CMP yield per area has never been developed, primarily due to the lack of (i) a general model of CMP architectures, and (ii) a practically-useable model for computing areas of chip versions with different numbers of spares. This paper develops such models and, in conjunction with a systematic approach for enumerating a wide range of spare configurations, uses these to compute area overhead and yield for each configuration. In particular, this paper proposes a k-way spare sharing technique to obtain optimal spare configurations which maximize yield per area of any CMP by efficiently traversing the design space for adding spares. Experimental results show significant yield per area improvements over the previous approaches and show that these benefits will continue to grow with increase in the levels of parallelism in CMPs as well as with continued technology scaling