Efficient Implementation of Precise Exception for Processor Based on Pre-detection

Embedded systems have higher requirements on real-time performance of processor. However exception, which can interrupt normal execution of program, will decrease the processor performance. For improving the exception handling efficiency of processor, a precise exception handling method for embedded pipeline processor based on pre-detection is proposed in this paper. When the precise exception occurs in any pipeline stage, the precise exception flag is set valid immediately and advanced to the next pipeline stage. Based on pre-detection on the exception flag, a single-cycle NOP instruction is provided for the processor by a dedicated hardware module. That separates the processor from spending large number of clock cycles requesting main instruction memory for instructions which will be flushed in the process of exception handling. This method has been implemented in a SPARC V8 processor which has successfully taped out. Test results of chip show that the precise exception detection and response efficiency is increased by 35.47% without increasing the processor critical path. The proposed method can be used to improve response efficiency of the precise exception at low hardware overheads. Keywords-exception flag; pre-detection; dedicated module; NOP instruction; processor