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A low-jitter multi-phase ADPLL for 3Gbps SerDes Transceivers in 0.18um CMOS
A low-jitter multi-phase ADPLL for 3Gbps SerDes Transceivers in 0.18um CMOS
2006
Seung-Hoon Jung
Kwang-Jin Lee
Yun Jeong Kim
Cheol Woong Kim
Uk-Rae Cho
Choong-guen Kwak
Hyun-Guen Byun
Suki Kim
Keywords:
SerDes
Jitter
Transceiver
CMOS
Electronic engineering
Engineering
multi phase
Electrical engineering
low jitter
Correction
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