Warpage Behavior Study and Optimization for Ultra-Thin POP Memory with Multi-Stacked Chips

The POP advanced electronic packaging type is widely used in high-end chips because of its huge advantages comparing to the traditional packaging. Electrically, POP offers benefits by minimizing track length between different chips or packages. This brings better electrical performance of devices, since shorter routing of interconnections yields faster signal propagation and reduced noise and cross-talk. Furthermore, it has both the flexibility of the supply chain and cost control for the system integration. Most importantly, the yield rate is guaranteed due to the bottom and upper components of the POP have been packaged and tested. However, as the chip size increasing and multi dies stacking, POP products will meet great technical challenges, among them, the warpage problem is one of the most important issues. With the ultra-thin trend of POP, the warpage will be too sensitive to predict empirically. There are many factors to affect warpage, including mold compound material and substrate selection, package structure design, and assembly process control etc. In this article, the FEA simulation model and warpage behavior are analyzed for ultrathin POP memory. To improve the model's prediction accuracy, the viscoelastic property of the mold compound material was measured and fitted, the results from the viscoelastic warpage models show well correlation with the shadow moire testing data. Factors sensitivity analysis are also studied for warpage prediction and optimization, which can guide the selection of the mold component material, substrate and optimization of the structure design.