A 12-bit 10 MS/s 12 mW pipelined SAR ADC for CubeSat systems using Vcm-based switching MDAC and unit capacitor array

Abstract This paper presents a 12-bit 10 MS/s pipelined successive approximation register (SAR) analog-to-digital converter (ADC) for a CubeSat system. A full differential architecture is adopted, and a single-ended-to-differential circuit is integrated in the ADC. The proposed ADC is divided into a first-stage 6-bit SAR-based multiplying digital–analog converter (MDAC) and a second-stage 8-bit SAR ADC. A new MDAC using a V cm -based switching method is employed to reduce power dissipation and improve the linearity of the ADC. Moreover, a unit capacitor array is used to improve the conversion speed and linearity of the first-stage MDAC. In addition, several radiation-hardened-by-design techniques are adopted in the layout design to protect against space radiation effects. A prototype chip was fabricated in a 0 . 18 μ m mixed-signal 1.8 V/3.3 V process and operated with a 1.8 V supply. The chip occupies a core area of 1 . 35 mm 2 . The proposed pipelined SAR ADC consumes 12 mW and achieves a peak signal-to-noise-and-distortion ratio of 65.8 dB and a peak spurious-free dynamic range of 78.5 dB at a sampling rate of 10 MS/s. The figure of merit of the proposed ADC is 0.75 pJ/conversion-step.