A 0.021 µm 2 trigate SRAM cell with aggressively scaled gate and contact pitch

We present the highest density demonstration of CMOS technology reported to date featuring a 6T SRAM cell size of 0.021 µm 2 (Fig. 1). The motivation for this work was to explore the limits of device patterning and basic module integration at dimensions relevant to the 10 nm node [1]. A trigate device architecture with a minimum contacted gate pitch (CGP) and minimum contacted fin pitch (CFP) of 50 nm was used as the target technology for this demonstration.