A smart design methodology for advanced memories

The authors propose a smart design methodology for advanced memories to reduce the turn around time for circuit revisions with no area penalty. This method was applied to the development of 16 Mb DRAM with double metal wiring. The turn around time can be reduced to 1/8 by 1500 gates of extra n-ch and p-ch transistors under the power line and the signal line. This design methodology is confirmed to be very effective. >