A Complementary Switched MOSFET Architecture for the 1/f Noise Reduction in Linear

We present a novel principle for noise reduction in linear analog CMOS ICs. The principle is experimentally demonstrated for a two-stage CMOS Miller operational amplifier in a standard 0.12- m, 1.5-V digital CMOS technology. A three- fold noise reduction (5 dB) is achieved at 10 Hz compared with a reference circuit. The impact of the principle on the circuit performance is investigated. Index Terms—CMOS linear analog IC, 1/f noise reduction, switched bias technique.