Designing Algorithm for the High Speed TIQ ADC, with Improved Accuracy

Differential nonlinearity (DNL) and integral nonlinearity (INL) are two main performance parameters for an analog-to-digital converter (ADC), which determine an ADC's static accuracy. Theoretically, an ideal ADC can be designed, which has zero nonlinearities. However, it is practically impossible due to manufacturing process variations. Although there were an ideal ADC, its real performance would not be ideal due to operating temperature and supply voltage variations when the ADC is deployed in non-ideal environments. With these variations, we present a new designing algorithm that will result in minimal nonlinearity of a flash ADC utilizing the Threshold Inverter Quantization (TIQ) voltage comparator circuits. The new proposed algorithm reduces worst-case nonlinearity of an 8-bit TIQ flash ADC by 77 percent in comparison to previous algorithms over manufacturing process variations. This new designing algorithm was implemented considering the discrete size (count of fins) and was programmed in a TIQ comparator section software package.