A $\mu$ Processor Layer for mm-Scale Die-Stacked Sensing Platforms Featuring Ultra-Low Power Sleep Mode at 125°C

This paper presents an ultra-low power sleep mode $\mu$ processor layer designed for use in mm-scale die-stacked wireless sensing platforms for high temperature applications. A compact DC-DC converter is incorporated with a 16kB custom SRAM for self-sufficient memory data retention, enabling a platform-level deep sleep mode. The proposed system is fabricated in a USJC 55nm deeply depleted channel (DDC) technology that is deliberately shifted to the slow corner, allowing the complete sensing platform to retain full memory contents with 0.54\mu\mathrm{W}$ during sleep mode at 125°C, which is 26× lower than without the proposed techniques.